1. Field of the Invention
The present invention relates to a thin film transistor device, a method of manufacturing the same, and a liquid crystal display device and, more particularly, a thin film transistor device formed on an insulating substrate of a liquid crystal display device, or the like, a method of manufacturing the same, and a liquid crystal display device.
2. Description of the Prior Art
The liquid crystal display device has features such as light weight, thin thickness, low power consumption, etc., and is put in practice in wide application fields such as the mobile terminal, the viewfinder of the video camera, the notebook-sized personal computer, etc. In particular, the active-matrix liquid crystal display device which uses thin film transistors (abbreviated to “TFTs” hereinafter) as the switching element is often employed in the applications such as the computer display or the like, which require the high-quality and high-definition display.
In the active-matrix liquid crystal display device, the TFT which uses the polysilicon film as the operating layer (referred to as the “pSi-TFT” hereinafter) is employed because of its high driving capability. In recent years, with the progress of the polysilicon film forming technology, the investigation on such a structure that the thin film transistors in the display region (referred to as “pixel TFTs” hereinafter) and the TFTs in the peripheral circuit portion except the display region are formed on the same substrate is now carried out with a view to achieving a lower cost and a higher function.
Since the pixel TFTs are used to drive the liquid crystal, the high voltage must be applied to their gates and drains. Thus, the high breakdown voltage against the gate voltage and the drain voltage is required of such pixel TFTs. On the contrary, the lower power consumption and the high-speed operation are required of the TFTs in the peripheral circuit portion.
In order to achieve this request, in Patent Application Publication (KOKAI) Hei 10-170953, etc., there has been proposed the example in which the pixel TFTs, whose gate insulating film is formed thick, and the TFTs in the peripheral circuit portion, whose gate insulating film is formed thin, are formed on the same substrate.
A sectional structure of the liquid crystal display device in which the thickness of the gate insulating film is different between the pixel TFTs and the TFTs in the peripheral circuit portion, which are formed on the same substrate, is shown in FIG. 1. In this case, the high voltage is also applied to some of the TFTs in the peripheral circuit portion, and thus the same structure as the pixel TFTs is employed in such TFTs in the peripheral circuit portion.
According to the above liquid crystal display device manufacturing method, the gate insulating film made of the silicon oxide film is formed on the island-like semiconductor films 4a, 4b made of the polysilicon film. At that time, the film thickness is adjusted by changing the number of laminated layers of the insulating films in the thick thickness portion and the thin thickness portion. More particularly, as described in the following, a number of insulating films are formed sequentially and also the unnecessary insulating films are etched.
That is, the first insulating film is formed on an overall surface of the substrate. Then, the first insulating film 5 in the TFT forming region in the thick thickness portion is left by the etching, but such first insulating film 5 in other regions is removed.
Then, the second insulating film and the metal film are formed in this order on the overall surface. Then, the metal film is patterned. Thus, in the TFT forming region in the thin thickness portion, the first gate electrode 7a is formed on the second insulating film 6a. Also, in the TFT forming region in the thick thickness portion, the second gate electrode 7b is formed on the laminated structure consisting of the first insulating film 5 and the second insulating film 6b. As a result, in the TFT forming region in the thin thickness portion, the first gate insulating film having the single-layer structure consisting of the second insulating film 6a is formed under the first gate electrode 7a. Also, in the TFT forming region in the thick thickness portion, the second gate insulating film having the double-layered structure consisting of the first and second insulating films 5, 6b is formed under the second gate electrode 7b. 
Also, in the TFT in the thick thickness portion, normally the deterioration in the ‘ON’ characteristic due to the hot carrier should be suppressed and the ‘OFF’ current should be reduced. For this reason, as shown in FIG. 5, the structure has the LDD (Lightly Doped Drain) structure in which the low-concentration impurity regions 4bc, 4bd are provided in regions between the channel region 4be under the gate electrode 75 and the high-concentration impurity regions 4ba, 4bb. If viewed from the upper side, the boundaries between the channel region 4be and the low-concentration impurity regions 4bc, 4bd, are positioned substantially just under the edges of the gate electrode 75. In some cases, the regions that correspond to the low-concentration impurity regions 4bc, 4bd may be formed as the offset region into which the impurity is not introduced.
The normal TFT is formed in the thin thickness portion, and the TFT having the LDD structures is formed in the thick thickness portion. Thus, as shown in FIG. 6A, in the TFT forming region in the thin thickness portion, first the first gate electrode 72 is formed on the first insulating film 71. Then, in the OFT forming region in the thick thickness portion, the resist mask 73a whose width is wider than the gate electrode forming region by the LDD region on one side is formed. Then, the ion is implanted by using the first gate electrode 72 and the resist mask 73a as a mask. Thus, the high-concentration impurity regions 4aa, 4ab are formed in the island-like semiconductor film 4a on both sides of the first gate electrode 72. Also, the high-concentration impurity regions 4ba, 4bb are formed in the island-like semiconductor film 4a on both sides of the resist mask 73a. 
Then, the resist mask 73a is removed. Then, as shown in FIG. 6B, in the TFT forming region in the thick thickness portion, the new resist mask 73b is formed in the region that is narrower than the region in which the resist mask 73a is formed. Then, the ion is implanted based on the resist mask 73b. Thus, the low-concentration impurity regions 4bc, 4bd are formed in the regions between the edges of the resist mask 73b and the edges of the high-concentration impurity regions 4ba, 4bb. In this case, the region that is sandwiched between the low-concentration impurity regions 4bc, 4bd acts as the channel region 4be. 
Then, the first insulating film 71 is etched by using the first gate electrode 72 and the resist mask 73b as a mask. Thus, as shown in FIG. 5, the first insulating film 71a is formed under the first gate electrode 72, and the first insulating film 71b is left under the resist mask 73b. Then, the resist mask 73b is removed, and then the second insulating film and the metal film are formed on the overall surface.
Then, the metal film is patterned. Thus, as shown in FIG. 5, in the TFT forming region in the thin thickness portion, the second gate electrode 75 is formed over the channel region 4be. Then, the second insulating film 74a is left by etching the second insulating film while using the second gate electrode 75 as a mask. Thus, the second gate insulating film having the double-layered structure consisting of the first and second insulating films 71b, 74a is formed under the second gate electrode 75.
Subsequently, the thin film transistor device shown in FIG. 5 can be formed via the normal steps. In this case, in FIG. 5, a reference 76 denotes the first interlayer insulating film, 76a to 76d denote the contact hole, 77a to 77d denote the source/drain electrodes, and 78 denotes the second interlayer insulating film.
However, in the manufacturing method in the prior art shown in FIG. 1, as shown in FIG. 2, the first insulating film 5 is etched by the dry etching method. In this case, the surface of the island-like semiconductor film 4a in the TFT forming region in the thin thickness portion, particularly the surface of the channel portion, is exposed to the plasma of the etching gas. Therefore, there is the problem such that, since the damage layer 13 is generated on the surface of the island-like semiconductor film 4a, characteristics of the TFT in the thin thickness portion are deteriorated rather than characteristics of the TFT in the thick thickness portion.
On the contrary, as shown in FIG. 3A, the first insulating film 5 is etched by the wet-etching method using the hydrofluoric acid, or the like. In this case, since it is difficult to get the selective etching ratio of the island-like semiconductor films 4a, 4b to the underlying silicon oxide film 3, such underlying silicon oxide film 3 is also etched at the time of over-etching. As a result, the “scraped portion” 14 is caused in the silicon oxide film 3 under the edge portions of the island-like semiconductor films 4a, 4b. 
In order to avoid this event, as shown in FIG. 3B, the second insulating film 6 and the metal film 7 serving as the gate electrode are formed and then, as shown in FIGS. 4A and 4B, the gate electrode 7a is formed by patterning the metal film 7 while using the resist mask 9c. If doing this, the crack is ready to occur in the second insulating film 6a at the scraped portions on the edge portions of the island-like semiconductor film 4a because the gate insulating film of the TFT in the thin thickness portion, which is formed of only the second insulating film 6a, is formed thin. As a result, there is the problem such that the gate breakdown voltage of the TFT in the thin thickness portion is extremely deteriorated.
In addition, the edge portion of the island-like semiconductor film 4a is tapered by the etching to have the top end with an acute angle. For this reason, unless the scraped portion is generated at the edge portion of the island-like semiconductor film 4a, the concentration of the electric field is caused particularly in the TFT in the thin thickness portion when the gate voltage is applied. Thus, there is the problem such that the so-called parasitic TFT is operated more quickly than the normal TFT.
Also, in order to prevent these events, there is employed such a structure that only the edge portions of the island-like semiconductor film 4a of the TFT in the thin thickness portion are covered. Normally, this structure is formed by using the mask-exposure from the upper surface of the substrate 1. In this case, the widths of the island-like semiconductor films 4a, 4b must be set large from a viewpoint of assuring the margin in the mask precision and the alignment precision. As a result, the limit is placed on the miniaturization of the TFT.
In addition, in the manufacturing method in the prior art shown in FIGS. 6A and 6B, the miniaturization makes progress. Therefore, it becomes difficult to form the LDD structure with holding the mutual arrangement among the high-concentration impurity regions 4ba, 4bb, the low-concentration impurity regions 4bc, 4bd, and the gate electrode 75. This prevents the miniaturization.
Further, the multi-layered insulating films 71b, 74a constituting the gate insulating film, as shown in FIG. 5, are etched by separate steps respectively. As a result, these steps take much time and labor, and thus the simplification of these steps is desired.